Very Large Scale Integration

CONTENTS

1. Introduction to Advanced Digital Design

1. Introduction

2. Review of Sequential Logic

2.1 Synchronous Sequential Logic Circuit

2.2 Asynchronous Sequential Logic Circuit

2.3 Metastability

2.4 Noise Margin

2.5 Power Dissipation

2.5 Finite State Machine

3. Moore and Mealy Models

3.1 State Machine Notation

2. Introduction to CMOS Technology

1. Introduction

2. Comparison of BJT and CMOS Parameters

3. Design of Basic Gates using CMOS

3.1 CMOS Inverter

3.2 CMOS NOR Gate

3.3 CMOS NAND Gate

3.4 MOS Transistor Switches

3.5 Transmission Gates

4. Drawing of Complex Logic using CMOS

5. Estimation of Layout Resistance and Capacitance

5.1 Resistance Estimation

5.2 Capacitance Estimation

5.3 Switching Characteristics

6. Fabrication Process

6.1 Overview of Wafer Processing

6.2 Oxidation

6.3 Epitaxy

6.4 Deposition

6.5 Ion Implementation

6.6 Diffusion

6.7 Silicon Gate Process

7. Basics of NMOS, PMOS and CMOS

7.1 The P-Well Process

7.2 The n-well Process

7.3 The Twin-Tub Process

3. Introduction to VHDL

1. Introduction

1.1 History of VHDL

1.2 Pro’s and Con’s of VHDL

2. Flow Elements of VHDL

2.1 Entity (Entity Declaration)

2.2 Architecture (Architecture Declaration)

2.3 Configuration (Configuration Declaration)

2.4 Package

2.5 Library

3. Data Types

3.1 Operators, Operations

4. Signal, Constant and Variable (Syntax and Use)

4. VHDL Programming

1. Introduction

2. Concurrent Constructs (When, With, Process)

2.1 When Statement or Construct

2.2 With Statement or Construct

2.3 Process Construct or Statement

3. Sequential Constructs (Process, If, Case, Loop, Assert, Wait)

3.1 If-Statement

3.2 Case Statement

3.3 Loop Statement

3.4 Assertion (Assert) Statement

3.5 WAIT Statement

4. Simple VHDL Program to Implement Flip-Flop, Counter Shift-register, Mux, Demux, Encoder, Decoder, Moore, Mealy Machines

5. Test Bench and its Applications

5.1 Applications of Test Bench

5. HDL Simulation and Synthesis

1. Introduction

2. Event Scheduling

3. Sensitivity List

4. Zero Modeling

5. Simulation Cycle

6. Comparison of Hardware and Software Description Language

7. Delta Delay

8. Types of Simulator Event Based and Cycle Based

8.1 Types of Simulator

8.2 Simulator Architecture

9. HDL Design Flow for Synthesis

9.1 Post Synthesis Design Flow

10. Efficient Coding Styles

10.1 Coding Style Requirements

11. Optimizing Arithmetic Expression

12. Sharing of Complex Operator

6. Introduction to ASIC, FPFA, PLD

1. Introduction

2. ASIC

2.1 ASIC Design Flow

3. CPLD

3.1 Xilinx 9500 Series CPLD

3.2 Atmel CPLD

4. Introduction of FPGA like Xilinx (FPGA) Spartan 3 Series and Atmel

4.1 Xilinx FPGA

4.2 Spartan 3 Series

4.3 Atmel FPGA