Contents
1. Number Systems and Digital Codes
1. Introduction
2. Decimal Number System
3. Binary Number System
3.1 Binary to Decimal Conversion
3.2 Decimal to Binary Conversion
4. Octal Number System
4.1 Decimal to Octal Conversion
4.2 Octal to Decimal Conversion
5. Octal to Binary Conversion
5.1 Binary to Octal Conversion
6. Hexadecimal Number System
6.1 Decimal to Hex Conversion
6.2 Hex to Decimal Conversion
6.3 Hex to Binary Conversion
6.4 Binary to Hex Conversion
6.5 Hex to Octal and Octal to Hex Conversion
7. Signed Number Representations
8. Binary Addition and Binary Subtraction using 2’s Complement
8.1 Binary Addition
8.2 Binary Subtraction
8.3 Subtraction using 1’s Complement
8.4 Subtraction using 2’s Complement
9. Weighted and Unweighted Codes
9.1 BCD Code (Weighted Code)
10. Excess – 3 Code
11. Gray Code (Unweighted Code)
11.1 Binary to Gray Conversion
11.2 Gray to Binary Conversion
12. Alphanumeric Representation
12.1 ASCII Code
2. Logic Gates
1. Logic Gates
1.1 Concept of Positive and Negative Logic
2. Basic Logic Gates
2.1 OR Gate
2.2 AND Gate
2.3 NOT Gate (Inverter Gate)
3. Derived Logic Gates
3.1 NOR Gate
3.2 NAND Gate
3.3 EX – OR Gate
3.4 EX – NOR Gate
4. Universal Gates
3. Logic Families
1. Introduction to CMOS and TTL Logic Families
1.1 Classification of Logic Families
1.2 Parameters of Logic Families
3. TTL Basic Gate, 2 Input TTL NAND Gate
4. CMOS Logic Family
4.1 CMOS NOT Gate
4. Boolean Algebra
1. Boolean Algebra Rules and Boolean Laws
1.1 Boolean Algebra Laws
1.2 Proofs of Some Laws
1.3 Boolean Algebra and Identities
2. De – Morgan’s Theorems
2.1 De Morgan’s 1st Theorem
2.2 De Morgan’s 2nd Theorem
3. Boolean Expression in SOP and POS Form, Min Term and Max Term
4. Conversion of SOP/POS Expression to its Standard SOP/POS Forms
4.1 SOP Boolean Expression
4.2 POS Boolean Expression
5. Introduction to Karnaugh Map
1. Introduction
2. Digital Designing using K-Map for: Gray to Binary and Binary to Gray Conversion
2.1 3 Bit Binary to Gray Converter
2.2 3 Bit Gray Code to Binary Converter
3. Parity Generator and Parity Checking
3.1 EXOR Gates as Parity Checker
6. Combinational Circuits
1. Introduction to Arithmetic Circuits
2. Half Adder
3. Full Adder
4. Half Subtractor
5. Full Subtractor
6. 4-bit Parallel Adder
7. Universal Adder – Subtractor
8. Digital Comparator
9. Introduction to ALU
10. Introduction to Combinational Circuits
11. Multiplexers
11.1 2 to 1 Multiplexer
11.2 4 to 1 Multiplexer
11.3 Tree Multiplexing
11.4 Multiplexer ICs
11.5 Multiplexer Applications
12. Demultiplexers
12.1 1 to 2 Demultiplexer using AND gates without strobe
12.2 1 to 4 Demultiplexer using AND gates without strobe
12.3 1 to 4 Demultiplexer using NAND gates with strobe
12.4 Demultiplexer ICs
12.5 Demultiplexer Applications
13. Encoders
13.1 Decimal to BCD/Binary Encoder
13.2 3 x 4 Matrix Keyboard Encoder
13.3 Priority Encoder IC 74148
14. Decoders
14.1 BCD to Decimal Decoder
14.2 BCD to 7 Segment Decoder

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